verilog 编译报错怎么解，谢谢

module lvds_tx_rx (
input sys_clk , //系统时钟
//input sys_clk_pn ,
input sys_rst_n , //系统复位
input clk_in_from_pin_p, //lvds时钟输出P
input clk_in_from_pin_n, //lvds时钟输入N
input clk_in_from_pin_p1,
input clk_in_from_pin_n1,
input data_in_from_pin_p, //lvds输入数据P
input data_in_from_pin_n, //lvds输入数据N
input data_in_from_pin_p1,
input data_in_from_pin_n1,
output clk_out_to_pin_p, //lvds时钟输出P
output clk_out_to_pin_n, //lvds时钟输出N
output data_out_to_pin_p, //lvds输出数据P
output data_out_to_pin_n //lvds输出数据N
);
wire p2s_div_8_clk; //串行发送时钟的8分频
wire s2p_div_8_clk; //串行接收时钟的8分频
wire s2p_div_8_clk1;
reg [7:0] tx_data;
wire [7:0] rx_data ; //LVDS输入的8位并行数据
wire [7:0] rx_data1 ;
reg [7:0] rx_data_dly1 ;
reg bitslip_en ;
reg data_equal;
//assign sys_clk_pn = sys_clk
//产生LVDS发送的测试数据，0~FF，循环累加计数
always @(posedge p2s_div_8_clk or negedge sys_rst_n) begin
if (~sys_rst_n)
tx_data <= 8'h0;
else
tx_data <= tx_data + 1'b1;
end
//产生BITSLIP信号，用于修改串转并的Bit的起始位置
// 数据打一拍，延迟一个周期
always @(posedge s2p_div_8_clk or negedge sys_rst_n) begin
if (~sys_rst_n)
rx_data_dly1 <= 8'h0;
else
rx_data_dly1 <= rx_data1 ;
end
always @(posedge s2p_div_8_clk or negedge sys_rst_n ) begin
if (~sys_rst_n) begin
bitslip_en <= 1'b0;
data_equal <=1'b0;
end
else if ( data_equal == 1'b0 ) begin
if( rx_data1 != 8'h81 && rx_data_dly1 == 8'h80 ) begin // 如果上次数据位80 当前数据不等于81，认为数据没有同步
bitslip_en <= 1'b1; // BITSLIP产生一个高脉冲，改变串转并的数据排列
data_equal <= 1'b0; // 数据正确信号为0
end
else begin
bitslip_en <= 1'b0; //BITSLIP不为高
data_equal <= 1'b1; //数据正确信号为1
end
end
else begin
bitslip_en <= 1'b0 ; //
data_equal <= data_equal ; // 保持
end
end
//并转串，8位数据tx_data转换成串行数据，并通过lvds差分信号输出，数据从FPGA送出管脚
uclk uclk_u0
(// Clock in ports
.CLK_IN1(clk_in_from_pin_p), // IN
// Clock out ports
.CLK_OUT1(clk_in_from_pin_p1), // OUT
.CLK_OUT2(clk_in_from_pin_n1),
// .CLK_OUT2(CLK_OUT2), // OUT
// .CLK_OUT3(CLK_OUT3), // OUT
// .CLK_OUT4(CLK_OUT4), // OUT
// .CLK_OUT5(CLK_OUT5), // OUT
// .CLK_OUT6(CLK_OUT6), // OUT
// Status and control signals
.RESET(sys_rst_n)// IN
//.LOCKED(LOCKED)
);
p2s p2s_u0
(
.DATA_OUT_FROM_DEVICE(tx_data ), //Input
.DATA_OUT_TO_PINS_P (data_out_to_pin_p), //Output
.DATA_OUT_TO_PINS_N (data_out_to_pin_n), //Output
.CLK_TO_PINS_P (clk_out_to_pin_p ), //Output
.CLK_TO_PINS_N (clk_out_to_pin_n ), //Output
.CLK_IN (sys_clk ), //Single ended clock from IOB
.CLK_DIV_OUT (p2s_div_8_clk ), //Slow clock output
.IO_RESET (~sys_rst_n ) //system reset
);
//串转并，LVDS差分信号转换成单端信号再通过串转并，转换为8位数据rx_data，数据从FPGA输入管脚
s2p s2p_u0
(
.DATA_IN_FROM_PINS_P(data_in_from_pin_p), // Input
.DATA_IN_FROM_PINS_N(data_in_from_pin_n), // Input
.DATA_IN_TO_DEVICE (rx_data ), // Output
.BITSLIP (bitslip_en ), // Input pin
.CLK_IN_P (clk_in_from_pin_p1 ), // Differential clock from IOB
.CLK_IN_N (clk_in_from_pin_n1 ), // Differential clock from IOB
.CLK_DIV_OUT (s2p_div_8_clk ), // Slow clock output
.IO_RESET (~sys_rst_n ) // system reset
);
s2p s2p_u1
(
.DATA_IN_FROM_PINS_P(data_in_from_pin_p1), // Input
.DATA_IN_FROM_PINS_N(data_in_from_pin_n1), // Input
.DATA_IN_TO_DEVICE (rx_data1 ), // Output
.BITSLIP (bitslip_en ),
.CLK_IN_P (clk_in_from_pin_p1 ), // Differential clock from IOB
.CLK_IN_N (clk_in_from_pin_n1 ), // Differential clock from IOB
.CLK_DIV_OUT (s2p_div_8_clk1 ), // Slow clock output
.IO_RESET (~sys_rst_n ) // system reset
);
// 添加ILA触发信号
wire [35:0] CONTROL0 ;
wire [63:0] TRIG0_DATA ;
chipscope_icon chipscope_icon_u0 (
.CONTROL0(CONTROL0)
);
chipscope_ila chipscope_ila_u0 (
.CONTROL(CONTROL0 ),
.CLK (s2p_div_8_clk ), // TRIG CLK
.TRIG0 (TRIG0_DATA ) // TRIG0 [63:0]
);
assign TRIG0_DATA[7:0] = tx_data ;
assign TRIG0_DATA[15:8] = rx_data1 ;
assign TRIG0_DATA[23:16] = rx_data_dly1 ;
assign TRIG0_DATA[24] = bitslip_en ;
assign TRIG0_DATA[25] = data_equal ;
endmodule