用Verilog HDL制作模可控的分频器，别的都正常，就是模6有问题！

module FDIV (CLK,K_OR1,K_OR2,K_OR3,K_OR4,K_OR5,K_OR6,K_OR7,K_OR8,s3,s2,s1,s0,y);
input CLK,s3,s2,s1,s0;
output K_OR1,K_OR2,K_OR3,K_OR4,K_OR5,K_OR6,K_OR7,K_OR8,y;
wire[3:0] SEL;
wire AT,BT,CT,DT,ET,FT,GT,HT;
reg[2:0]C1,C2; reg M1,M2;
reg[2:0]C3,C4; reg M3,M4;
reg[2:0]C5,C6; reg M5,M6;
reg[1:0]B1; reg N1;
reg[1:0]B2; reg N2;
reg[1:0]B3; reg N3;
reg[1:0]B4; reg N4;
assign SEL={s3,s2,s1,s0};
assign AT=(SEL==4'D1); assign BT=(SEL==4'D2);
assign CT=(SEL==4'D3); assign DT=(SEL==4'D4);
assign ET=(SEL==4'D5); assign FT=(SEL==4'D6);
assign GT=(SEL==4'D7); assign HT=(SEL==4'D8);
assign y=(K_OR1&AT)|(K_OR2&BT)|(K_OR3&CT)|(K_OR4&DT)|(K_OR5&ET)|(K_OR6&FT)|(K_OR7&GT)|(K_OR8&HT);
assign K_OR1=CLK; //NO1
always @(negedge CLK) begin
if(B1==1) begin N1<=~N1; B1<=0; end else if(B1==0) begin N1=~N1; B1<=B1+1; end end
assign K_OR2=N1; //NO2
always @(posedge CLK) begin
if(C3==2) begin C3<=0; M3<=~M3;end else C3<=C3+1;
if(C3==1) M3<=~M3; end
always @(negedge CLK) begin
if(C4==2) begin C4<=0; M4=~M4;end else C4<=C4+1;
if(C4==1) M4<=~M4; end
assign K_OR3=M3|M4; //NO3
always @(negedge CLK) begin
if(B2==3) begin B2<=0; N2=~N2; end else B2<=B2+1;
if(B2==1) N2<=~N2; end
assign K_OR4=N2; //NO4
always @(posedge CLK) begin
if(C1==4) C1<=0; else C1<=C1+1;
if(C1==1) M1<=~M1; else if(C1==3) M1=~M1; end
always @(negedge CLK) begin
if(C2==4) C2<=0; else C2<=C2+1;
if(C2==1) M2<=~M2; else if(C2==3) M2=~M2; end
assign K_OR5=M1|M2; //NO5
always @(negedge CLK) begin
if(B3==5) begin B3<=0; N3=~N3; end else B3<=B3+1;
if(B3==2) N3<=~N3; end
assign K_OR6=N3; //NO6
always @(posedge CLK) begin
if(C5==6) C5<=0; else C5<=C5+1;
if(C5==1) M5<=~M5; else if(C5==4) M5=~M5; end
always @(negedge CLK) begin
if(C6==6) C6<=0; else C6<=C6+1;
if(C6==1) M6<=~M6; else if(C6==4) M6=~M6; end
assign K_OR7=M5|M6; //NO7
always @(negedge CLK) begin
if(B4==7) begin B4<=0; N4=~N4; end else B4<=B4+1;
if(B4==3) N4<=~N4; end
assign K_OR8=N4; //NO8
endmodule
大神们帮忙看看哪有错啊，模6的时候模拟的波形成8分频的了。。查了半天也看不出哪错了