的6位密码锁 电脑里没VHDL程序 编译不了 求大神帮我编译一下 看报不报错 波形图
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ctrl is
port
(change,vers,keysign: in std_logic;
ok,cancel: in std_logic;
clk: in std_logic;
result: in std_logic;
wt: in std_logic;
enable: out std_logic
);
end ctrl;
architecture ctrl_behave of ctrl is
signal sec : integer range 0 to 60;
begin
process(clk)
begin
if (clk'event and clk='1') then
if (vers='1') then
enable<='1';
end if;
if (wt='1' and result='1') then
enable<='0';
sec<=0;
end if;
if (change='0' and vers='0' and keysign='0' and ok='0' and cancel='0') then
sec<=sec+1;
if (sec=59) then
enable<='0';
sec<=0;
end if;
else
sec<=0;
end if;
end if;
end process;
end ctrl_behave;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ver is
port
(dt1,dt2,dt3,dt4,dt5,dt6: in std_logic_vector(3 downto 0);
cd1,cd2,cd3,cd4,cd5,cd6: in std_logic_vector(3 downto 0);
vers: in std_logic;
ready: in std_logic;
clk: in std_logic;
stopalarm: in std_logic;
en: in std_logic;
result: out std_logic;
wrong: out std_logic;
alarm: out std_logic
);
end ver;
architecture ver_behave of ver is
signal alarmnum : integer range 0 to 3;
signal vering : std_logic;
signal wronging: std_logic;
begin
process(clk)
begin
if (clk'event and clk='1') then
if (en='0') then
result<='0';
end if;
if (stopalarm='1') then
alarmnum<=0;
end if;
if (wronging='1') then
wronging<='0';
vering<='1';
end if;
if (alarmnum<3) then
alarm<='0';
else
alarm<='1';
end if;
if (vers='1') then
vering<='1';
end if;
if (vering='1') then
if (ready='1') then
if (cd1=dt1 and cd2=dt2 and cd3=dt3 and cd4=dt4 and cd5=dt5 and cd6=dt6) then
result<='1';
else
result<='0';
wronging<='1';
if (alarmnum<3) then
alarmnum<=alarmnum+1;
end if;
end if;
vering<='0';
end if;
end if;
elsif (clk'event and clk='0') then
if (wronging='1') then
wrong<='1';
elsif (wronging='0') then
wrong<='0';
end if;
end if;
end process;
end ver_behave;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity code is
port
(dt1,dt2,dt3,dt4,dt5,dt6: in std_logic_vector(3 downto 0);
change: in std_logic;
ready: in std_logic;
ok: in std_logic;
clk: in std_logic;
result: in std_logic;
reset: in std_logic;
wt: out std_logic;
cd1,cd2,cd3,cd4,cd5,cd6: out std_logic_vector(3 downto 0)
);
end code;
architecture code_behave of code is
signal alarmnum : integer range 0 to 3;
signal changing : std_logic;
signal changed: std_logic;
signal wting: std_logic;
begin
process(clk)
begin
if (clk'event and clk='1') then
if (ok='1' and changing='0' and result='1') then
wting<='1';
else
wting<='0';
end if;
if (reset='1') then
cd1<="1001";
cd2<="1001";
cd3<="1001";
cd4<="1001";
cd5<="1001";
cd6<="1001";
end if;
if (change='1') then
changing<='1';
end if;
if (changing='1') then
if (ready='1') then
if (result='1') then
cd1<=dt1;
cd2<=dt2;
cd3<=dt3;
cd4<=dt4;
cd5<=dt5;
cd6<=dt6;
wting<='1';
end if;
changing<='0';
end if;
end if;
elsif (clk'event and clk='0') then
if (wting='1') then
wt<='1';
else
wt<='0';
end if;
end if;
end process;
end code_behave;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity keyboard is
port
(a3,a2,a1,a0: in std_logic;
a: out std_logic_vector(3 downto 0);
k: in std_logic;
keysign: out std_logic;
clk: in std_logic
);
end keyboard;
architecture keyboard_behave of keyboard is
begin
process(clk)
begin
if (clk'event and clk='0') then
a(3)<=a3;
a(2)<=a2;
a(1)<=a1;
a(0)<=a0;
keysign<=k;
end if;
end process;
end keyboard_behave;
2
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity keyin is
port
(en: in std_logic;
clk: in std_logic;
a: in std_logic_vector(3 downto 0);
keysign: in std_logic;
ok: in std_logic;
cancel: in std_logic;
ver: in std_logic;
ready: out std_logic;
dt1,dt2,dt3,dt4,dt5,dt6: out std_logic_vector(3 downto 0)
);
end keyin;
architecture keyin_behave of keyin is
signal count : integer range 0 to 7;
signal cready : std_logic;
begin
process(en,clk,keysign)
begin
if (en='1') then
if (clk'event and clk='1') then
if (keysign='1' and count<6) then
count<=count+1;
if (count=0) then
dt1<=a;
elsif(count=1) then
dt2<=a;
elsif(count=2) then
dt3<=a;
elsif(count=3) then
dt4<=a;
elsif(count=4) then
dt5<=a;
elsif(count=5) then
dt6<=a;
end if;
end if;
if (ver='1') then
count<=0;
end if;
if (cancel='1') then
count<=0;
dt1<="1111";
dt2<="1111";
dt3<="1111";
dt4<="1111";
dt5<="1111";
dt6<="1111";
end if;
if (ok='1') then
count<=0;
cready<='1';
else
cready<='0';
end if;
elsif (clk'event and clk='0') then
if (cready='1') then
ready<='1';
else
ready<='0';
end if;
end if;
end if;
end process;
end keyin_behave;